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US7773495B2 · kind B2 · utility

2Cited by
1References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 12, 2005
Grant dateAug 10, 2010
Priority date
Expiry dateNov 7, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11B20/00086
  • WIPO fieldAudio-visual technology
  • WIPO sectorElectrical engineering

Abstract

The invention relates to a memory authentication method based on a pattern of storage areas of said memory that have altered latencies that are respectively altered such that the respective alteration of the latency of a storage area lies within a measurement noise of latency measurements in respect to the standard latency of said storage area when the measurement is performed with a reading device for accessing said record medium. The verification is then performed by a correlation of the latencies of the altered storage areas with a key used to alter the storage areas.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.