Timeout acceleration for globally shared memory transaction tracking table
US7774562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2004 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jun 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.