Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests
US7774563B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Dec 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, data processing system, and computer usable program code are provided for reducing memory access latency. A memory controller receives a memory access request and determines if an address associated with the memory access request falls within an address range of a plurality of paired memory address range registers. The memory controller determines if an enable bit associated with the address range is set to 1 in response to the address falling within one of the address ranges. The memory controller flags the memory access request as a high-priority request in response to the enable bit being set to 1 and places the high-priority request on a request queue.A dispatcher receives an indication that a memory bank is idle. The dispatcher determines if high-priority requests are present in the request queue and, if so, sends the earliest high-priority request to the idle memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.