Method to control core duty cycles using low power modes
US7774626B2 · kind B2 · utility
18Cited by
4References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3228
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.