Patent · US Active

LDPC decoder for DVB-S2 decoding

US7774674B2 · kind B2 · utility

3Cited by

5References

21Claims

0Family size

Assignee

STMICROELECTRONICS N.V. · NL

Inventors

Norbert Wehn · Queidersbach, DE
Frank Kienle · Edenkoben, DE
Torben Brack · Kaiserslautern, DE

Key dates

Filing date	Mar 2, 2006
Grant date	Aug 10, 2010
Priority date	—
Expiry date	Jan 8, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6566
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.