Method of fabricating high-k metal gate devices
US7776757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2009 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Jan 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.