Method and apparatus for selecting demodulation processing delays in a receiver
US7778312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03515
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver includes a baseband processor for selecting a set of demodulation processing delays for received signal demodulation from a larger set of candidate delays. In one embodiment, the baseband processor selects the set of demodulation processing delays by calculating at least one metric for each demodulation processing delay in the set of candidate delays, iteratively reducing the set of candidate delays by eliminating one or more demodulation processing delays from the set as a function of comparing the metrics, and setting the processing delays for received signal demodulation to the candidate delays remaining after reduction. In a Generalized RAKE (G-RAKE) embodiment, the metric corresponds to combining weight magnitudes associated with G-RAKE finger delays. In a chip equalizer embodiment, the metric corresponds to coefficient magnitudes associated with equalization filter tap delays. In other embodiments, the metric corresponds to Signal to Interference Ratios (SIRs) associated with the set of candidate delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.