Sampling rate mismatch solution
US7778373B2 · kind B2 · utility
3Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Jan 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow the rate of data through the buffer. In sample addition, pseudo samples are inserted into a data stream to compensate for timing differences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.