Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction
US7778815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Sep 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.