System and method to reduce memory latency in microprocessor systems connected with a bus
US7779188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Apr 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1615
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.