System and method for reducing power consumption in a data processor having a clustered architecture
US7779240B2 · kind B2 · utility
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Inventors
Key dates
| Filing date | Sep 14, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.