Mechanism to enhance and enforce multiple independent levels of security in a microprocessor memory and I/O bus controller
US7779254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | May 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a system and a method for extending multiple independent levels of security to a plurality of input/output buses and components connected to the buses. In an exemplary embodiment, the system may include a processing unit suitable for operation in a plurality of security level. A bus controller including security control logic may be coupled to the processing unit for restricting access and flow of information between the physical memory and the plurality of buses. The bus controller may employ base address registers to allocate and map the physical memory to control which partitions of the physical memory are accessible to each of the plurality of buses and thus, a device connected to at least one of the plurality of buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.