Error processing across multiple initiator network
US7779308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Aug 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/0659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for error log processing is provided. Each error log is given a defined priority and mapped to an error recovery procedure (ERP) to be run if the log is seen. The system has a plurality of software layers to process the errors. Each software layer processes the error independently. Errors are reported to a higher software stack when error recovery fails from the lower stack ERPs and recovery is non-transparent. If the system host identified for error processing fails, the control of the ERP is transferred during the failover process. Non-obvious failed component isolating ERPs are grouped to be run together to assist in isolating the failed component. Prioritization of the error systems may be based on a plurality of criteria. ERPs are assigned to run within a particular software stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.