Method of testing memory array at operational speed using scan
US7779316B2 · kind B2 · utility
3Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Dec 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.