Systems and methods for tri-column code based error reduction
US7779331B2 · kind B2 · utility
16Cited by
40References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Mar 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.