Deinterleaver and dual-viterbi decoder architecture

US7779338B2 · kind B2 · utility

Assignee

• REALTEK SEMICONDUCTOR CORP. · TW

Inventors

• Mustafa Altintas · Irvine, US
• Turgut Aytur · Oakland, US
• Ravishankar H. Mahadevappa · Irvine, US
• Feng Shi · Beijing, CN
• Stephan ten Brink · Allmersbach im Tal, DE
• Ran-Hong Yan · Leyland, GB

Key dates

• Filing date: Jul 21, 2006
• Grant date: Aug 17, 2010
• Expiry date: Mar 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L1/06
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.