Task scheduling method for low power dissipation in a system chip
US7779412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | May 15, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.