Semiconductor process evaluation methods including variable ion implanting conditions
US7781234B2 · kind B2 · utility
0Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Feb 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.