Method of fabricating semiconductor interconnections
US7781339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76867
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.