Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
US7782673B2 · kind B2 · utility
13Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes memory cells, a source line, a word line, a bit line, and a driver circuit. The memory cells are formed on a semiconductor layer and have a charge accumulation layer and a control gate on the charge accumulation layer. The word line is connected to gate of the memory cell. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The driver circuit varies potential of the semiconductor layer in conjunction with potential of the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.