Power gating circuit, system on chip circuit including the same and power gating method
US7782701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Aug 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.