Hardware device data buffer
US7783823B2 · kind B2 · utility
0Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Dec 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits associated with at least one of the data packets in one of a plurality of addressable locations of the data buffer. The system further comprises a pointer memory configured to store a respective pointer associated with each of the plurality of addressable locations of the data buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.