System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer
US7783835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2008 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Jun 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.