Method and apparatus for controlling memory system
US7783840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2004 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Dec 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.