Vertical and horizontal pipelining in a system for performing modular multiplication
US7783864B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Jan 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/722
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the chaining together of processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a pardonable chain with separate parts for processing factors of the modulus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.