Programmable logic device
US7783897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Jun 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/60
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A hardware decryption processor operates, when power is applied to a programmable logic device, to read an encrypted configuration program, to decrypt the encrypted configuration program using a first secret configuration key stored in a register, and to configure a programmable array of logic elements with the configuration program. The programmable array when configured with the configuration program operates to read the encrypted configuration program from a non-volatile store, to decrypt the configuration program using the first secret configuration key, which was provided with the configuration program, to generate a second secret key, to adapt the configuration program by inserting the second secret key into the configuration program, to re-encrypt the adapted configuration program using the first secret configuration key, and to replace the configuration program with the adapted and encrypted configuration program in the non-volatile store.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.