Electrical parameter extraction for integrated circuit design
US7783999B2 · kind B2 · utility
11Cited by
17References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2008 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Jun 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.