Non-volatile semiconductor memory device and method of manufacturing the same
US7785964B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.