Process for integrating a III-N type component on a (001) nominal silicium substrate
US7785991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2007 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Sep 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/01335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.