Method for fabricating self-aligned complementary pillar structures and wiring
US7786015B2 · kind B2 · utility
22Cited by
37References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Apr 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.