Reduction of charge leakage from a thyristor-based memory cell
US7786505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2005 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/031
Abstract
Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.