Analog to digital converter with improved input overload recovery
US7786909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Dec 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.