Correlation-based background calibration of pipelined converters with reduced power penalty
US7786910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.