Digital phase locked loop with dithering
US7786913B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | May 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.