Packet unstopper system for a parallel packet switch
US7787446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5682
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.