Interleaver with linear feedback shift register
US7788560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2008 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Aug 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.