Adjustable test pattern results latency
US7788564B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2007 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Feb 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.