Displaying cache information using mark-up techniques
US7788642B2 · kind B2 · utility
9Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2006 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.