Clock distribution techniques for channels
US7791370B1 · kind B1 · utility
26Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | May 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.