Method and system for FET-based amplifier circuits
US7791410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2008 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, a method is implemented using a field-effect transistor (FET) having a gate node, a source node and a drain node. A first circuit state is implemented in which the gate node, the source node and the drain node are connected to inputs that generate a stored charge at the gate node, the amount of stored charge at the gate node being responsive to a first voltage level. A second circuit state is implemented in which the drain node is connected to a voltage source, the source node is connected to a load, and while charge at the gate node is preserved, current between the drain node to the source node drives a voltage level of the load to a proportionally amplified version of the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.