Memory integrated circuit device providing improved operation speed at lower temperature
US7791959B2 · kind B2 · utility
9Cited by
8References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Apr 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory integrated circuit device may include a first temperature sensing unit, a first voltage adjusting unit, and a MOS back bias voltage outputting unit. The first voltage adjusting unit may be configured to output a voltage based on an output signal of the temperature sensing unit such that the voltage output changes based on changes in a sensed temperature. The MOS back bias voltage outputting unit may be configured to receive the voltage output by the voltage adjusting unit and configured to output the MOS back bias voltage based on the voltage output by the first voltage adjusting unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.