High-speed FIR filters in FPGAs
US7793013B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, circuits, and an apparatus for filtering high-speed serial data is disclosed. In one embodiment, a Programmable Logic Device (PLD) is configured with a filter circuit for filtering serial data at a first clock rate. The filter circuit converts an N number of serial data streams into an N number of M-bit words based on a deserialization factor. The M-bit words are converted to an M number of N-bit data words. The N-Bit data words are filtered at a second clock rate, reformatted, serialized, and outputted as individual serial data streams at the first clock rate. In one embodiment, the N-bit data words are digitally filtered by a Finite Impulse Response (FIR) filter operating at the second clock rate. The data output of the FIR filter is then serialized into an N number of serial data output streams operating at the first clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.