Memory architecture with serial peripheral interface
US7793031B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.