Partial page scheme for memory technologies
US7793037B2 · kind B2 · utility
6Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2005 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Dec 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.