Method and apparatus for power throttling a processor in an information handling system
US7793125B2 · kind B2 · utility
33Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Mar 21, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.