Mother/daughter switch design with self power-up control
US7793130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2007 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Mar 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.