Efficient memory product for test and soft repair of SRAM with redundancy
US7793173B2 · kind B2 · utility
10Cited by
5References
3Claims
0Family size
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Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Aug 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.