Semiconductor memory device
US7793192B2 · kind B2 · utility
4Cited by
7References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2005 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device (1) comprising a nonvolatile memory (2) having a data writing unit smaller than a physical block is provided with an error detecting/correcting circuit (23) in the non-volatile memory (2). When data stored in a specified block of the non-volatile memory (2) is transferred to a different physical block and written, the error detecting/correcting circuit (23) performs error detection and correction of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.