Per processor set scheduling
US7793293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Sep 7, 2010 |
| Priority date | — |
| Expiry date | Mar 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.