Patent · US Active

Method and apparatus for a configurable protection architecture for on-chip systems

US7793345B2 · kind B2 · utility

29Cited by
21References
26Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 27, 2005
Grant dateSep 7, 2010
Priority date
Expiry dateDec 4, 2028

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Various methods and apparatuses of protection mechanism are described. A target intellectual property block may field and service requests from an initiator intellectual property block in a system-on-chip network. The target intellectual property block has an associated protection mechanism with logic configured to restrict access for the requests to the target intellectual property block. The request's access is restricted based on access permissions associated with a region within the target intellectual property block and attributes of the request trying to access that region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.